Back Compute Express Link Catalan Compute Express Link Finnish Compute Express Link Japanese 컴퓨트 익스프레스 링크 Korean Compute Express Link Chinese
 | |
| Year created | 2019 |
|---|---|
| Created by | Intel |
| No. of devices | 4096 |
| Speed | Full duplex 1.x, 2.0 (32 GT/s):
3.x (64 GT/s):
|
| Style | Serial |
| Website | www |
Compute Express Link (CXL) is an open standard interconnect for high-speed, high capacity central processing unit (CPU)-to-device and CPU-to-memory connections, designed for high performance data center computers.[1][2][3][4] CXL is built on the serial PCI Express (PCIe) physical and electrical interface and includes PCIe-based block input/output protocol (CXL.io) and new cache-coherent protocols for accessing system memory (CXL.cache) and device memory (CXL.mem). The serial communication and pooling capabilities allows CXL memory to overcome performance and socket packaging limitations of common DIMM memory when implementing high storage capacities.[5][6]
- ^ "ABOUT CXL". Compute Express Link. Retrieved 2019-08-09.
- ^ "Synopsys Delivers Industry's First Compute Express Link (CXL) IP Solution for Breakthrough Performance in Data-Intensive SoCs". finance.yahoo.com. Yahoo! Finance. Retrieved 2019-11-09.
- ^ "A Milestone in Moving Data". Intel Newsroom. Intel. Retrieved 2019-11-09.
- ^ "Compute Express Link Consortium (CXL) Officially Incorporates; Announces Expanded Board of Directors". www.businesswire.com. Business Wire. 2019-09-17. Retrieved 2019-11-09.
- ^ "StackPath". www.electronicdesign.com. 13 October 2021. Retrieved 2023-02-03.
- ^ Mann, Tobias (2022-12-05). "Just How Bad Is CXL Memory Latency?". The Next Platform. Retrieved 2023-02-03.