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Memory access pattern

In computing, a memory access pattern or IO access pattern is the pattern with which a system or program reads and writes memory on secondary storage. These patterns differ in the level of locality of reference and drastically affect cache performance,[1] and also have implications for the approach to parallelism[2][3] and distribution of workload in shared memory systems.[4] Further, cache coherency issues can affect multiprocessor performance,[5] which means that certain memory access patterns place a ceiling on parallelism (which manycore approaches seek to break).[6]

Computer memory is usually described as "random access", but traversals by software will still exhibit patterns that can be exploited for efficiency. Various tools exist to help system designers[7] and programmers understand, analyse and improve the memory access pattern, including VTune and Vectorization Advisor,[8][9][10][11][12] including tools to address GPU memory access patterns.[13]

Memory access patterns also have implications for security,[14][15] which motivates some to try and disguise a program's activity for privacy reasons.[16][17]

  1. ^ "Introduction to Data-Oriented Design" (PDF). Archived from the original (PDF) on 2019-11-16.
  2. ^ Jang, Byunghyun; Schaa, Dana; Mistry, Perhaad & Kaeli, David (2010-05-27). "Exploiting Memory Access Patterns to Improve Memory Performance in Data-Parallel Architectures". IEEE Transactions on Parallel and Distributed Systems. 22 (1). New York: IEEE: 105–118. doi:10.1109/TPDS.2010.107. eISSN 1558-2183. ISSN 1045-9219. S2CID 15997131. NLM unique id 101212014.
  3. ^ Jeffers, James; Reinders, James; Sodani, Avinash (2016-05-31). Intel Xeon Phi Processor High Performance Programming: Knights Landing Edition (2nd ed.). Morgan Kaufmann. ISBN 9780128091951.
  4. ^ Jana, Siddhartha; Schuchart, Joseph; Chapman, Barbara (2014-10-06). "Analysis of Energy and Performance of PGAS-based Data Access Patterns" (PDF). Proceedings of the 8th International Conference on Partitioned Global Address Space Programming Models. PGAS '14. New York, NY, USA: Association for Computing Machinery. pp. 1–10. doi:10.1145/2676870.2676882. ISBN 978-1-4503-3247-7.
  5. ^ Marandola, Jussara; Louise, Stéphane; Cudennec, Loïc; Acquaviva, Jean-Thomas; Bader, David (2012-10-11). "Enhancing Cache Coherent Architectures with access patterns for embedded manycore systems". 2012 International Symposium on System on Chip (SoC) (PDF). IEEE. pp. 1–7. doi:10.1109/ISSoC.2012.6376369. ISBN 978-1-4673-2896-8.
  6. ^ "intel terascale" (PDF).
  7. ^ Brown, Mary; Jenevein, Roy M.; Ullah, Nasr (29 November 1998). Memory Access Pattern Analysis. WWC '98: Proceedings of the Workload Characterization: Methodology and Case Studies (published 1998-11-29). p. 105. ISBN 9780769504506.
  8. ^ Ostadzadeh, S. Arash; Meeuws, Roel J.; Galuzzi, Carlo; Bertels, Koen (2010). "QUAD – A Memory Access Pattern Analyser" (PDF). In Sirisuk, Phaophak; Morgan, Fearghal; El-Ghazawi, Tarek; Amano, Hideharu (eds.). Reconfigurable Computing: Architectures, Tools and Applications. Lecture Notes in Computer Science. Vol. 5992. Berlin, Heidelberg: Springer. pp. 269–281. doi:10.1007/978-3-642-12133-3_25. ISBN 978-3-642-12133-3.
  9. ^ Che, Shuai; Sheaffer, Jeremy W.; Skadron, Kevin (2011-11-12). "Dymaxion: Optimizing memory access patterns for heterogeneous systems" (PDF). Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis. SC '11. New York, NY, USA: Association for Computing Machinery. pp. 1–11. doi:10.1145/2063384.2063401. ISBN 978-1-4503-0771-0.
  10. ^ Harrison, Luddy (1996-01-01). "Examination of a memory access classification scheme for pointer-intensive and numeric programs". Proceedings of the 10th international conference on Supercomputing - ICS '96. New York, NY, USA: Association for Computing Machinery. pp. 133–140. doi:10.1145/237578.237595. ISBN 978-0-89791-803-9.
  11. ^ Matsubara, Yuki; Sato, Yukinori (2014). "Online Memory Access Pattern Analysis on an Application Profiling Tool". 2014 Second International Symposium on Computing and Networking. pp. 602–604. doi:10.1109/CANDAR.2014.86. ISBN 978-1-4799-4152-0. S2CID 16476418.
  12. ^ "Putting Your Data and Code in Order: Data and layout".
  13. ^ Kim, Yooseong; Shrivastava, Aviral (2011-06-05). "CuMAPz: A tool to analyze memory access patterns in CUDA". Proceedings of the 48th Design Automation Conference. DAC '11. New York, NY, USA: Association for Computing Machinery. pp. 128–133. doi:10.1145/2024724.2024754. ISBN 978-1-4503-0636-2.
  14. ^ Kim, Yooseong; Shrivastava, Aviral (2011-06-05). "CuMAPz: A tool to analyze memory access patterns in CUDA". Proceedings of the 48th Design Automation Conference. DAC '11. New York, NY, USA: Association for Computing Machinery. pp. 128–133. doi:10.1145/2024724.2024754. ISBN 978-1-4503-0636-2.
  15. ^ Canteaut, Anne; Lauradoux, Cédric; Seznec, André (2006). Understanding cache attacks (report thesis). INRIA. ISSN 0249-6399.
  16. ^ Hardesty, Larry (2013-07-02). "Protecting data in the cloud". MIT News.
  17. ^ Rossi, Ben (2013-09-24). "Boosting cloud security with oblivious RAM". Information Age.

Memory access pattern

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